Breakdown strength, reliability and lifetime of III-nitride power semiconductor devices such as gallium nitride (GaN) devices are reduced by high electric fields in the devices. Conventional field plate fabrication processes can reduce electrical fields in power semiconductor devices, but are not sufficient for many applications. As a consequence, device dimensions such as gate-drain distance or dielectric thickness are often increased to avoid premature device breakdown at high voltages and circumvent reliability and lifetime issues. However, increased gate-drain distance and dielectric thickness leads to increased cost and deterioration of switching characteristics. As such, there is a need for power semiconductor devices with a more homogeneous potential distribution at the source, drain and gate contacts and in the drift region of the device, respectively.